jgrogan/stuff-from-scratch
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Toward core module compiling.

Browse source
This commit is contained in:
jmsgrogan 2023-12-27 12:20:02 +00:00
parent c25a56ee19
commit 3ed195d7dd
305 changed files with 1774 additions and 1065 deletions
Download patch file Download diff file Expand all files Collapse all files

2
plugins/circuits/src/CircuitElement.h
View file

@ -1,7 +1,7 @@
#pragma once
#include "String.h"
#include "Memory.h"
#include "Pointer.h"
class CircuitElement

2
plugins/circuits/src/ElectronicCircuit.h
View file

@ -1,6 +1,6 @@
#pragma once
#include "Memory.h"
#include "Pointer.h"
#include "Vector.h"
#include "CircuitElement.h"

6
plugins/circuits/src/TruthTable.h
View file

@ -8,7 +8,7 @@ class TruthTable
public:
using TableData = std::map<Vector<bool>, Vector<bool> >;
TruthTable(std::size_t, std::size_t)
TruthTable(size_t, size_t)
//: mNumInputColumns(numInputColumns),
// mNumOutputColumns(numOutputColumns)
{
@ -25,8 +25,8 @@ public:
static const TruthTable::TableData AND_TRUTH_TABLE;
private:
//std::size_t mNumInputColumns{ 0 };
//std::size_t mNumOutputColumns{ 0 };
//size_t mNumInputColumns{ 0 };
//size_t mNumOutputColumns{ 0 };
TableData mTable;
};

14
plugins/circuits/src/gates/LogicGate.cpp
View file

@ -1,6 +1,6 @@
#include "LogicGate.h"
NInMOutLogicGate::NInMOutLogicGate(std::size_t numIn, std::size_t numOut, Vector<Wire*> inputs, Vector<Wire*> outputs)
NInMOutLogicGate::NInMOutLogicGate(size_t numIn, size_t numOut, Vector<Wire*> inputs, Vector<Wire*> outputs)
: LogicGate(),
mNumIn(numIn),
mNumOut(numOut)
@ -24,17 +24,17 @@ NInMOutLogicGate::NInMOutLogicGate(std::size_t numIn, std::size_t numOut, Vector
}
}
std::size_t NInMOutLogicGate::getNumInputs() const
size_t NInMOutLogicGate::getNumInputs() const
{
return mNumIn;
}
std::size_t NInMOutLogicGate::getNumOutputs() const
size_t NInMOutLogicGate::getNumOutputs() const
{
return mNumOut;
}
Wire* NInMOutLogicGate::getInput(std::size_t idx) const
Wire* NInMOutLogicGate::getInput(size_t idx) const
{
if (idx < mNumIn)
{
@ -46,7 +46,7 @@ Wire* NInMOutLogicGate::getInput(std::size_t idx) const
}
}
Wire* NInMOutLogicGate::getOutput(std::size_t idx) const
Wire* NInMOutLogicGate::getOutput(size_t idx) const
{
if (idx < mNumOut)
{
@ -58,7 +58,7 @@ Wire* NInMOutLogicGate::getOutput(std::size_t idx) const
}
}
void NInMOutLogicGate::setAtInput(std::size_t idx, Wire* value)
void NInMOutLogicGate::setAtInput(size_t idx, Wire* value)
{
if (idx < mInputs.size())
{
@ -66,7 +66,7 @@ void NInMOutLogicGate::setAtInput(std::size_t idx, Wire* value)
}
}
void NInMOutLogicGate::setAtOutput(std::size_t idx, Wire* value)
void NInMOutLogicGate::setAtOutput(size_t idx, Wire* value)
{
if (idx < mOutputs.size())
{

28
plugins/circuits/src/gates/LogicGate.h
View file

@ -4,7 +4,7 @@
#include "TruthTable.h"
#include "Wire.h"
#include "Memory.h"
#include "Pointer.h"
#include "Vector.h"
class LogicGate : public CircuitElement
@ -20,13 +20,13 @@ public:
};
virtual ~LogicGate() = default;
virtual std::size_t getNumInputs() const = 0;
virtual size_t getNumInputs() const = 0;
virtual std::size_t getNumOutputs() const = 0;
virtual size_t getNumOutputs() const = 0;
virtual Wire* getInput(std::size_t idx) const = 0;
virtual Wire* getInput(size_t idx) const = 0;
virtual Wire* getOutput(std::size_t idx) const = 0;
virtual Wire* getOutput(size_t idx) const = 0;
virtual const TruthTable& getTruthTable() = 0;
@ -41,25 +41,25 @@ public:
class NInMOutLogicGate : public LogicGate
{
public:
NInMOutLogicGate(std::size_t numIn, std::size_t numOut, Vector<Wire*> inputs = {}, Vector<Wire*> outputs = {});
NInMOutLogicGate(size_t numIn, size_t numOut, Vector<Wire*> inputs = {}, Vector<Wire*> outputs = {});
virtual ~NInMOutLogicGate() = default;
std::size_t getNumInputs() const override;
size_t getNumInputs() const override;
std::size_t getNumOutputs() const override;
size_t getNumOutputs() const override;
Wire* getInput(std::size_t idx) const override;
Wire* getInput(size_t idx) const override;
Wire* getOutput(std::size_t idx) const override;
Wire* getOutput(size_t idx) const override;
void setAtInput(std::size_t idx, Wire* value);
void setAtInput(size_t idx, Wire* value);
void setAtOutput(std::size_t idx, Wire* value);
void setAtOutput(size_t idx, Wire* value);
private:
std::size_t mNumIn{ 1 };
std::size_t mNumOut{ 1 };
size_t mNumIn{ 1 };
size_t mNumOut{ 1 };
Vector<Wire*> mInputs;
Vector<Wire*> mOutputs;

4
plugins/circuits/src/visuals/ElectronicCircuitNode.cpp
View file

@ -37,12 +37,12 @@ void ElectronicCircuitNode::buildWireConnections()
for (auto gate : mContent->getLogicGates())
{
for (std::size_t idx = 0; idx < gate->getNumInputs(); idx++)
for (size_t idx = 0; idx < gate->getNumInputs(); idx++)
{
mWireInputConnections[gate->getInput(idx)] = gate;
}
for (std::size_t idx = 0; idx < gate->getNumOutputs(); idx++)
for (size_t idx = 0; idx < gate->getNumOutputs(); idx++)
{
mWireOutputConnections[gate->getOutput(idx)] = gate;
}

8
plugins/circuits/src/visuals/ElectronicCircuitNode.h
View file

@ -4,7 +4,7 @@
#include "ElectronicCircuit.h"
#include <unordered_map>
#include Map.h
class WireNode;
class TerminalNode;
@ -36,8 +36,8 @@ private:
Vector<Ptr<WireNode> > mWireNodes;
Vector<Ptr<LogicGateNode> > mLogicGateNodes;
std::unordered_map<Wire*, CircuitElement*> mWireInputConnections;
std::unordered_map<Wire*, CircuitElement*> mWireOutputConnections;
Map<Wire*, CircuitElement*> mWireInputConnections;
Map<Wire*, CircuitElement*> mWireOutputConnections;
std::unordered_map<CircuitElement*, CircuitElementNode*> mNodesForContent;
Map<CircuitElement*, CircuitElementNode*> mNodesForContent;
};

6
plugins/circuits/src/visuals/LogicGateNode.cpp
View file

@ -21,9 +21,9 @@ LogicGateNode::~LogicGateNode()
Point2 LogicGateNode::getConnectionLocation(Wire* wire) const
{
bool is_input{ false };
std::size_t connection_id{ 0 };
size_t connection_id{ 0 };
for (std::size_t idx = 0; idx < mContent->getNumInputs(); idx++)
for (size_t idx = 0; idx < mContent->getNumInputs(); idx++)
{
if (mContent->getInput(idx) == wire)
{
@ -33,7 +33,7 @@ Point2 LogicGateNode::getConnectionLocation(Wire* wire) const
}
}
for (std::size_t idx = 0; idx < mContent->getNumOutputs(); idx++)
for (size_t idx = 0; idx < mContent->getNumOutputs(); idx++)
{
if (mContent->getOutput(idx) == wire)
{

4
plugins/circuits/src/visuals/LogicGatePrimitiveShapes.cpp
View file

@ -5,7 +5,7 @@ String LogicGatePrimitiveShapes::getAndGateShape()
return "M4 8 h24 a16 16 0 0 1 0 32 h-24Z";
}
Point2 LogicGatePrimitiveShapes::getAndGateConnectionLocation(bool isInput, std::size_t idx)
Point2 LogicGatePrimitiveShapes::getAndGateConnectionLocation(bool isInput, size_t idx)
{
if (isInput)
{
@ -29,7 +29,7 @@ String LogicGatePrimitiveShapes::getOrGateShape()
return "M4 8 h16 q16 2 24 16 q-12 16 -24 16 h-16 q12 -16 0 -32Z";
}
Point2 LogicGatePrimitiveShapes::getOrGateConnectionLocation(bool isInput, std::size_t idx)
Point2 LogicGatePrimitiveShapes::getOrGateConnectionLocation(bool isInput, size_t idx)
{
if (isInput)
{

4
plugins/circuits/src/visuals/LogicGatePrimitiveShapes.h
View file

@ -7,11 +7,11 @@
class LogicGatePrimitiveShapes
{
public:
static Point2 getAndGateConnectionLocation(bool isInput, std::size_t idx);
static Point2 getAndGateConnectionLocation(bool isInput, size_t idx);
static String getAndGateShape();
static Point2 getOrGateConnectionLocation(bool isInput, std::size_t idx);
static Point2 getOrGateConnectionLocation(bool isInput, size_t idx);
static String getOrGateShape();
};